Invited Speakers and Talks
Prof. Maurice Herlihy
Computer Science, Brown University, USA
Title: Locks, Transactions, and Concurrent Objects
Abstract: Software transactional memory (STM) is intended to make concurrent programs easier to design, implement, and reason about. STM is supported, either directly or through libraries, by an increasing number of languages and compilers, such as GNU C++, Clojure, Haskell, Java, Scala, and others. Perhaps inspired by databases, most STM synchronization and recovery mechanisms work by classifying operations as reads or writes. We argue that such an approach is unlikely to scale, especially for highly-contended "hot-spot" objects. As an alternative, we describe "transactional boosting", a technique for making highly-concurrent thread-safe data structures transactional. As long as the thread-safe implementation satisfies certain regularity properties (informally, that every method has an inverse), we define a simple wrapper transformation that that concurrent transactions without inherent conflicts can synchronize at the same granularity as the original thread-safe implementation.
Bio: Maurice Herlihy has an A.B. in Mathematics from Harvard University, and a Ph.D. in Computer Science from M.I.T. He has served on the faculty of Carnegie Mellon University, on the staff of DEC Cambridge Research Lab, and is currently a professor in the Computer Science Department at Brown University. He is the recipient of the 2003 Dijkstra Prize in Distributed Computing, the 2004 Gödel Prize in theoretical computer science, the 2008 ISCA influential paper award, the 2012 Edsger W. Dijkstra Prize, and the 2013 Wallace McDowell award. He received a 2012 Fulbright Distinguished Chair in the Natural Sciences and Engineering Lecturing Fellowship, and he is fellow of the ACM and a member of the National Academy of Engineering.
Date: Keynote plenary talk - Feb. 12th, 2014 (1st day)
Dr. Panagiotis Tsarchopoulos
Project Officer, Future and Emerging Technologies, DG CONNECT, European Commission
Title: High-Performance Computing in Horizon 2020
Abstract: Horizon 2020 is the new European Framework Programme for Research and Innovation that will run from 2014 to 2020. The talk will give an overview of Horizon 2020 and will discuss the perspectives for High-Performance Computing in Horizon 2020.
Date: Keynote plenary talk - Feb. 13th, 2014 (2nd day)
Dr. PhD. Piero Altoè
HPC Sales Manager, E4 Computer Engineering, Italy
Title: Who can beat x86?
Abstract: Nowadays the datacenter are more and more power-hungry and ARM based solutions can be the key to satisfy the power-saving cravings. E4 computer Engineering design server based on ARM and ARM+GPU architectures. A full technical description of the available products together with benchmarks and tests will be shown. In addition, a look at future developments within the ARM server will be explained in depth and cover topics such as: fast interconnection, computing power, application development. Our unique hardware can combine the Cortex processors with the computing power of the modern GPU, in an extremely dense and efficient solution. Test of FFT, matrix multiplication, n-body, and many more have been carried out with remarkable results.
E4 Computer Engineering web page
Date: Keynote plenary talk - Feb. 14th, 2014 (3rd day)
Dr. Francois Thomas
IBM HPC Specialist, Deep Computing Europe, IBM Client Center Montpellier, France
Title: Energy Aware Computing
Abstract: Power consumption is a critical factor for servers and data centers but do you know how much power your servers use and how much energy your applications consume , in which part of the server this power is consumed , and what can we do to reduce it ? After an introduction on the different sources of power consumption in a data center (power consumption, cooling and power loss), we will dig into the different components of the power consumption in a server when applications are executing. We will show the relation between power consumption and performance, progress accomplished through different processor generations and how we can take advantage of the trade-off between power and performance. In a last part, we will present the features we introduced in IBM Load Leveler which have been in production since June 2012 on SuperMUC at LRZ, Germany and the features which are been recently introduced in IBM Platform Computing LSF this year to implement Energy Aware Scheduling on x86 systems to control and optimize power and energy consumption of clusters running parallel applications.
Date: Keynote plenary talk - Feb. 14th, 2014 (3rd day)
Dr. Emilio Billi
CTO of A3Cube Inc., San Jose, CA, USA
Title: Massively Parallel Data Processor: breaking through the storage barrier
Abstract: Modern datacenters, high performance computing and high performance data systems require a new level of performance. Specifically, high-performance parallel computing technologies have become popular into the datacenter and industry for commercial research and development operations, (e.g. Hadoop), but there is a gap in the CPU power and data storage technologies that limits the efficiency of the entire datacenter ecosystem. We can call this enormous problem: I/O Performance Gap Problem. From a business point of view this means an order of magnitude greater energy expenses and total cost of management to satisfy the growing number of users. At the same time, the current datacenter infrastructure is not efficiently servicing current users-customers and today storage equipment is not ready to address emerging data analytics challenges.
Bio: Emilio Billi is IEEE member, chairman of the Hypertransport Consortium, and co-designer of the Hypertransport Hypershare Technology. He is co-founder e CTO of A3CUBE Inc (San Jose, California). He holds 4 US patents (with over 10 patents pending), he authored a number of scientific publications in the area of networking and parallel computer architecture.
Date: Keynote plenary talk - Feb. 14th, 2014 (3rd day)
